The invention relates generally to semiconductor devices and systems for designing and fabricating such devices, particularly to improving device layout in existing and anticipating new technology nodes, more particularly, to broadening an envelope of acceptable design elements to include layouts eliminated under existing methodologies that might actually be useful and manufacturable.
An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers typically design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include: (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC.
To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts. Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements, but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
Constraining factors in traditional photolithographic processes limit their effectiveness as circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., die shrink). Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain pitch, distance, and other such physical manufacturing constraints.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a wafer is severely limited by the pitch.
With the advance of ultra deep submicron technology, the feature size and feature pitch get so small that existing lithography processes meet their bottleneck in printing the shapes represented by the features. On the other hand, there are difficulties in the practical use of advanced photolithographic processes (e.g., extreme ultra violet (EUV)). Therefore, the current lithography technology is expected to be used for next generation silicon technology. To compensate for the difficulty in printing the shape of small pitches, multiple patterning lithography is recognized as a promising solution for 32 nm, 22 nm, 16 nm, and finer pitches as technology may allow in volume IC production. Multiple patterning lithography technology generally decomposes a single layer of a layout into multiple masks and applies multiple exposures to print the shapes in the layer. However, even multiple pattern lithography has limitations.
Due to inherent difficulties in sub-resolution lithography and modeling of resist processes, the risk of patterns which fail (either by short circuits, opens, or parametric failure) is substantially increased compared to the historical record. The standard industry practice of design rules checking (DRC) has become very difficult to implement due to the number and complexity of required rules and strong possibility that they are either too restrictive for efficient design or fail to detect patterns which will fail. For example, a layout or pattern including one or more “hotspots” based on pitch and other factors may be eliminated despite the pattern actually being useful and manufacturable. In many cases these patterns will be novel (different from what is known), and thus not known to be handled by the existing process stack and/or resolution enhancement techniques, such as optical proximity correction (OPC).
One proposed conservative approach to the layout rules problem is to restrict the allowable local patterns to a set which were previously demonstrated to be manufacturable, at least in a given shape context, on a test site or by rigorous simulation. A pattern is defined as a local region or window of layout, with the window size typically matched to an underlying routing or device grid and width up to a typical “optical radius,” within which the strongest influence of proximity effects on a layout are contained. Subsequent design layouts U must be scanned and compared with the known pattern library X, which, for a large number of layout patterns, yields a matching or distance operation with a complexity X*U, in a naïve implementation. Hierarchical cluster or tree matching can reduce this, but, especially for automatically routed layout systems with window sizes approaching the optical radius, the number of existing patterns on the new layout U can be quite large. For example, projections of a number of unique patterns based on layout scans of ungridded 22 nanometer data for optical radius sized windows can be as high as 500 million. As a result of these large numbers of patterns and associated computations, processor load for conventional distance-based matching techniques is very high, and might require runtime of distance-based novelty detection on the order of a CPU year.
Another approach is to change the manner in which layouts are created by EDA in the first place.